Case Studies

Projects

Deep dives into RTL design problems, SoC integration work, and design automation tooling. Each case study covers architecture decisions, implementation details, and measured results.

ASIC Optimization: AES-128 & JPEG Encoder on Nangate45

Complete

Synthesis-driven optimization of two IP blocks — AES-128 and a JPEG encoder — using Yosys 0.52 + ABC against the Nangate45 45nm standard-cell library. AES pipelining achieved +194% Fmax and 32× throughput. JPEG reciprocal-multiply quantization cut area 17.5% and QNR latency 73%.

RTL Verilog ASIC Yosys Synthesis Nangate45 AES JPEG Timing Closure

Find First Set Bit: Three RTL Architectures

Complete

Three independent SystemVerilog implementations of Find First Set Bit: sequential FSM, parallel combinational binary tree, and 6-stage pipeline. Synthesized against a 7nm-approximate library. 10,071 Icarus vectors and 66,536 Verilator vectors per design. Zero failures.

RTL SystemVerilog Digital Design ASIC Yosys Verilator

AMBA AXI4 Interconnect

Complete

Fully synthesizable, parameterized 2×2 non-blocking crossbar in SystemVerilog connecting two AXI4 masters to dual synchronous SRAM slaves, targeting 250 MHz on Xilinx UltraScale+.

SystemVerilog AXI4 AMBA RTL FPGA ASIC Crossbar