Resume
Akshay Prasad
GPU RTL Hardware Engineer · San Jose, CA
Results-driven GPU RTL Hardware Engineer with 5+ years of experience in the semiconductor industry, specializing in high-performance GPU architecture, RTL integration, and top-tier quality assurance. Currently at Samsung Semiconductor (SARC/ACL), focused on GPU top-level configurations, RTL quality sign-off, and cross-functional design bring-up. Expertise spans the full ASIC design flow, with deep specialization in RTL integration, LINT/CDC cleanliness, formal equivalence verification, and Python/Perl-driven automation.
Professional Experience
GPU RTL Integration Engineer
Samsung Semiconductor (SARC / ACL) · San Jose, CA
Jan 2023 – Present
- – Developed and validated multiple GPU top-level configurations to meet specific performance requirements. Managed the RTL database via Perforce and led cross-functional design bring-up.
- – Guided floorplan-driven connectivity for Multiple Instance Modules (MIM) and unique tiles to optimize feed-through routing, reduce global congestion, and minimize layout synthesis effort for the PD team. Mapped the logical daisy-chaining of debug buses, SLM telemetry (ProteanTecs), and memory power controls directly to physical tile placement.
- – Developed, owned, and maintained Jenkins regression jobs for RTL quality sign-off, executing VCS, Xcelium (xrun), LINT, CDC, DC/FC elaboration, and SG-DFT checks. Conducted formal equivalence checking (LEC) to validate logical vs. tiled and behavioral vs. structural netlists.
- – Delivered high-quality RTL to Physical Design and SoC teams, providing essential design collateral (including UPF and IP-XACT) to ensure efficient hand-offs and seamless integration, while collaborating closely with DV and Emulation teams to secure sign-off prior to milestone releases.
- – Partnered with Synopsys engineers to upgrade LINT and CDC tool versions and refine ruleset tags, proactively improving design methodologies. Developed custom Python and Perl scripts to automate regression runs and streamline workflow tasks.
Design Automation Engineer | Multi-Product Shuttle Engineer (MPS)
Intel Corporation · Hillsboro, OR
Jun 2020 – Jan 2023
- – Defined and implemented verification scripts and flows using Python and Perl, including automated quality checks and flow optimizations, ensuring MPS product design seats met full-chip tape-out requirements with high accuracy.
- – Developed CAD automation tools for physical design verification, including Design Rule Check (DRC), layout synthesis, and validation, enhancing design accuracy and efficiency.
- – Designed die-rings (Etch-ring, EDM, and PRS) for various die sizes and filler seats for multi-node technologies, supporting the Shuttle program.
- – Provided comprehensive customer support during tape-out executions, assisting with design rules, layout collaterals, and requirements.
Education
M.S. Electrical and Electronics Engineering
Arizona State University · Tempe, AZ
Aug 2018 – May 2020
B.E. Electronics and Communications Engineering
Dayananda Sagar Institutions · Bengaluru, India
Aug 2014 – May 2018
The Entrepreneurial Edge
London Business School · London, UK
Jun 2022 – Oct 2022
Academic & Research Experience
Graduate Teaching Assistant — VLSI Design (EEE 525)
Arizona State University · Phoenix, AZ
Jan 2020 – May 2020
Graduate Teaching Assistant — Analog Integrated Circuits (EEE 433/591)
Arizona State University · Arizona
Aug 2019 – Dec 2019
Teaching Assistant — Python for Rapid Engineering Solutions (EEE 498/591)
Arizona State University · Tempe, AZ
Jan 2019 – Aug 2019
Project Intern
Indian Institute of Technology, Guwahati · Guwahati, India
Developed a fault-tolerant routing algorithm for Mesh Network-on-Chip; published at VDAT-2018.
Jan 2018 – Jun 2018
Skills & Tools
RTL & Design
Architecture
EDA — Simulation
EDA — Synthesis
EDA — Analysis
Languages
Version Control
AI & Tooling
Certifications
Purple Certification: SystemVerilog For RTL Design
Synopsys Inc
Purple Certification: ASIC Design Flow
Synopsys Inc
Purple Certification: VDSM Fundamentals
Synopsys Inc
Purple Certification: CMOS Fundamentals
Synopsys Inc
Purple Certification: Digital Design Fundamentals
Synopsys Inc
Purple Certification: VLSI Basics
Synopsys Inc
Claude Code 101: From Prompt to Product
AI Coding Agents with GitHub Copilot and Cursor
PCAP – Certified Associate in Python Programming
OpenEDG Python Institute
PCEP – Certified Entry-Level Python Programmer
OpenEDG Python Institute
Computer Organization and Architecture
NPTEL
Publication
Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on Chip
22nd International Symposium on VLSI Design and Test (VDAT-2018)
Developed a routing algorithm built over the standard XY algorithm for fault-tolerant NoC communication.