GPU RTL Hardware Engineer

Akshay Prasad

Results-driven GPU RTL Hardware Engineer with 5+ years of experience in high-performance GPU architecture, RTL design, and quality assurance. Currently at Samsung driving full-chip RTL integration, regression infrastructure, and sign-off for production GPUs.

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Core Expertise

GPU RTL Design & Integration

ASIC Design Flow

RTL Quality & Sign-off

Design Automation

Formal Equivalence Checking

LINT & CDC Analysis

Featured Projects

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ASIC Optimization: AES-128 & JPEG Encoder on Nangate45

Complete

Synthesis-driven optimization of two IP blocks — AES-128 and a JPEG encoder — using Yosys 0.52 + ABC against the Nangate45 45nm standard-cell library. AES pipelining achieved +194% Fmax and 32× throughput. JPEG reciprocal-multiply quantization cut area 17.5% and QNR latency 73%.

RTL Verilog ASIC Yosys Synthesis Nangate45 AES JPEG Timing Closure

Find First Set Bit: Three RTL Architectures

Complete

Three independent SystemVerilog implementations of Find First Set Bit: sequential FSM, parallel combinational binary tree, and 6-stage pipeline. Synthesized against a 7nm-approximate library. 10,071 Icarus vectors and 66,536 Verilator vectors per design. Zero failures.

RTL SystemVerilog Digital Design ASIC Yosys Verilator

AMBA AXI4 Interconnect

Complete

Fully synthesizable, parameterized 2×2 non-blocking crossbar in SystemVerilog connecting two AXI4 masters to dual synchronous SRAM slaves, targeting 250 MHz on Xilinx UltraScale+.

SystemVerilog AXI4 AMBA RTL FPGA ASIC Crossbar